Wednesday 05 March 2025
Scientists have developed a new approach to building artificial intelligence (AI) accelerators, which could lead to significant improvements in the efficiency and speed of AI processing.
The team behind the research has designed a novel systolic array architecture that enables faster computation and lower energy consumption for matrix multiplication and convolution operations. These are essential components of many AI algorithms, including those used for image recognition, natural language processing, and machine learning.
The traditional approach to building AI accelerators involves using general-purpose computing architectures, such as graphics processing units (GPUs) or central processing units (CPUs). However, these architectures were not designed specifically for AI workloads and can be inefficient in terms of energy consumption and performance.
In contrast, systolic arrays are optimized for matrix multiplication and convolution operations, which are the building blocks of many AI algorithms. A systolic array is a type of digital circuit that consists of an array of processing elements (PEs) connected together in a regular pattern. Each PE performs a specific operation on a set of input data, and the outputs from each PE are fed into other PEs to perform more complex operations.
The team’s new architecture, called Axon, uses a novel data orchestration technique that enables faster computation and lower energy consumption. In traditional systolic arrays, data is propagated through the array in a linear fashion, which can lead to delays and inefficiencies. The Axon architecture, on the other hand, allows for bi-directional propagation of data, which reduces the delay and improves the overall performance of the system.
The team also developed an im2col hardware support that enables the acceleration of convolution operations. This is achieved by mapping a 3D tensor to a 2D matrix, which can be processed more efficiently using systolic arrays.
The results of the study show that the Axon architecture outperforms traditional systolic arrays in terms of computation speed and energy efficiency. The team’s design also requires less hardware overhead compared to other state-of-the-art designs.
The implications of this research are significant, as it could lead to more efficient and powerful AI accelerators that can be used in a wide range of applications, from robotics and autonomous vehicles to healthcare and finance. The development of more efficient AI accelerators is critical for the widespread adoption of AI technology, as it will enable faster processing times and lower energy consumption.
Cite this article: “Accelerating Artificial Intelligence: A Novel Systolic Array Architecture for Efficient Matrix Multiplication and Convolution Operations”, The Science Archive, 2025.
Artificial Intelligence, Ai Accelerators, Systolic Arrays, Matrix Multiplication, Convolution Operations, Graphics Processing Units, Central Processing Units, Digital Circuits, Data Orchestration, Im2Col Hardware Support.
