Tuesday 08 April 2025
The quest for efficient global routing in electronic design automation (EDA) has been ongoing for decades. As transistors shrink and integrated circuits become increasingly complex, finding ways to quickly and accurately route signals between components is crucial for designing reliable and high-performance chips.
Researchers have long employed various techniques to tackle this challenge, from maze-routing algorithms to machine learning-based approaches. Now, a new paper proposes an innovative solution that combines the strengths of both worlds: obstacle-avoiding global routing using rule-based OARSMT (Obstacle-Avoiding Rectilinear Steiner Minimal Tree) and sparse maze routing.
The problem with traditional global routing is that it often gets stuck in local optima, where the algorithm becomes trapped in a suboptimal solution due to obstacles or constraints. To overcome this limitation, the authors introduce an initial routing step using OARSMT, which generates a rough but obstacle-free route for each net (a connection between components). This approach allows for more efficient and accurate exploration of the design space.
The second part of the algorithm is sparse maze routing, which refines the initial route by iteratively exploring the neighborhood of the current best solution. By using a sparse graph representation, this step reduces the complexity of the routing problem and enables faster convergence to a high-quality solution.
Experiments on various benchmarks demonstrate the effectiveness of this hybrid approach. Compared to state-of-the-art algorithms, it achieves significant improvements in wirelength, via count, and overflow cost while maintaining reasonable runtime performance. For example, on a set of modified ISPD 2024 benchmarks, the proposed method reduces wirelength by an average of 1.96% and overflow cost by 28.06%.
The authors also explore the impact of different graph representations on the algorithm’s performance. They find that using dense graphs for maze routing can lead to slower convergence and reduced accuracy, while sparse graphs offer a better trade-off between exploration and exploitation.
This research has important implications for the development of next-generation EDA tools. As chip designs continue to increase in complexity, efficient global routing will be essential for ensuring reliable and high-performance operation. The proposed algorithm provides a promising solution that can handle large-scale designs with complex obstacles and constraints.
In addition to its technical merits, this work highlights the importance of interdisciplinary collaboration between computer scientists, electrical engineers, and mathematicians. By combining insights from geometry, graph theory, and machine learning, researchers can develop innovative solutions that tackle some of the most pressing challenges in EDA.
Cite this article: “Efficient Obstacle-Avoiding Global Routing with OARSMT Guidance”, The Science Archive, 2025.
Electronic Design Automation, Global Routing, Obstacle-Avoiding, Rule-Based Oarsmt, Sparse Maze Routing, Wirelength, Via Count, Overflow Cost, Graph Representation, Machine Learning
