Friday 28 February 2025
The article describes a new approach to designing System-on-Chip (SoC) architectures, which are the building blocks of modern electronics. The design combines the high-speed Advanced High-performance Bus (AHB) and the low-power Advanced Peripheral Bus (APB) into a single bridge that enables seamless communication between fast components and slower peripherals.
The AHB is typically used for high-speed operations, connecting processors and memory, while the APB is optimized for low-power, low-speed peripheral devices. The new bridge design converts complex AHB transactions into simpler, single-cycle APB transactions, allowing data to be transferred efficiently between different parts of a system.
The article highlights the challenges faced by designers when trying to integrate high-performance and low-power components within a single SoC. The bridge’s ability to handle clock domain synchronization, transaction conversion, and flow control ensures compatibility between AHB’s burst transfers and APB’s non-pipelined protocol.
To implement this design, researchers used Verilog modules for protocol conversion and Xilinx Vivado Design Suite for behavioral simulation and initial synthesis. They also utilized Synopsys DC Compiler for gate-level synthesis, providing detailed analysis of area, power, and timing.
The results show that the bridge design achieves a significant reduction in power consumption while maintaining performance. The combined use of Vivado, DC Compiler, and SPI-based communication establishes a robust, scalable, and power-efficient solution for bridging high-performance AHB subsystems with low-power APB peripherals.
The article concludes by highlighting the practicality and relevance of this approach in modern SoC designs, particularly in applications where both high-speed and low-power components are required.
Cite this article: “Integrating High-Speed and Low-Power Components with a Novel System-on-Chip Bridge Design”, The Science Archive, 2025.
System-On-Chip, Advanced High-Performance Bus, Advanced Peripheral Bus, Bridge Design, Protocol Conversion, Clock Domain Synchronization, Transaction Conversion, Flow Control, Low-Power, High-Performance.
